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toshiba confidential TC58NVG2D4BFT00 2004-07-13c 1 tentative toshiba mos digital inte grated circuit silicon gate cmos 4 gbit (512m 8 bit) cmos nand e 2 prom (multi level cell) description the tc58nvg2d4b is a single 3.3 v 4 gbit (4,429,185,024 bits) nand electrically erasable and programmable read-only memory (nand e 2 prom) organized as (2048 + 64) bytes 128 pages 2048 blocks. the device has two 2112-byte static registers which allow program and read data to be transferred between the register and the memory cell array in 2112-byte increments. the erase operation is implemented in a single block unit (256 kbytes + 8 kbytes: 2112 bytes 128 pages). the tc58nvg2d4b is a serial-type memory device whic h utilizes the i/o pins for both address and data input/output as well as for command in puts. the erase and program operations are automatically executed making the device most suitable for applications such as solid-state file storage, voice recordin g, image file memory for still cameras and other systems which require high-d ensity non-volatile memory data storage. features ? organization tc58nvg2d4b memory cell array 2112 256k 8 register 2112 8 page size 2112 bytes block size (256k + 4k) bytes ? modes read, read with data cache, reset, auto page progra m, auto page program with data cache, multi page program with cache, auto block erase, status read, page copy ? mode control serial input/output command control ? number of valid blocks max 2048 blocks min 1968 blocks ? power supply v cc = 2.7 v to 3.6 v ? program/erase cycles tbd cycles (with 4bit/528byte ecc) ? access time cell array to register 50 s max serial read cycle 50 ns min ? program/erase time auto page program 800 s/page typ. auto block erase 3 ms/block typ. ? operating current read (50 ns cycle) 10 ma typ. program (avg.) 10 ma typ. erase (avg.) 10 ma typ. standby 50 a max ? package TC58NVG2D4BFT00 tsop i 48-p-1220-0.50 (weight: 0.53 g typ.) free datasheet http:///
toshiba confidential TC58NVG2D4BFT00 2004-07-13c 2 pin assignment (top view) pinnames i/o1 to i/o8 i/o port ce chip enable we write enable re read enable cle command latch enable ale address latch enable psl power on select wp write protect by / ry ready/busy v cc power supply v ss ground TC58NVG2D4BFT00 nc nc nc nc i/o8 i/o7 i/o6 i/o5 nc psl nc v cc v ss nc nc nc i/o4 i/o3 i/o2 i/o1 nc nc nc nc 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 nc nc nc nc nc nc by / ry re ce nc nc v cc v ss nc nc cle ale we wp nc nc nc nc nc 8 8 free datasheet http:///
toshiba confidential TC58NVG2D4BFT00 2004-07-13c 3 block diagram absolute maximum ratings symbol rating value unit v cc power supply voltage ? 0.6 to 4.6 v v in input voltage ? 0.6 to 4.6 v v i/o input /output voltage ? 0.6 v to v cc + 0.3 v ( 4.6 v) v p d power dissipation 0.3 w t solder soldering temperature (10 s) 260 c t stg storage temperature ? 55 to 150 c t a operating ambient temperature 0 to 70 c capacitance * (ta = 25c, f = 1 mhz) symb0l parameter condition min max unit c in input v in = 0 v ? 10 pf c out output v out = 0 v ? 10 pf * this parameter is periodically samp led and is not tested for every device. i/o control circuit status register address register command register column buffer column decoder data register sense amp memory cell array control circuit hv generator row address decoder logic control by / ry v cc i/o1 v ss i/o8 psl ce cle ale we re by / ry row address buffer decoder to wp free datasheet http:///
toshiba confidential TC58NVG2D4BFT00 2004-07-13c 4 valid blocks symbol parameter min typ. max unit n vb number of valid blocks 1968 ? 2048 blocks note: the device occasionally contains unus able blocks. refer to application note (13) toward the end of this document. the first block (block 0) is guaranteed to be a valid block at the time of shipment. the minimum number of valid blocks is guaranteed over the lifetime. recommended dc operating conditions symbol parameter min typ. max unit v cc power supply voltage 2.7 v ? 3.6 v v v ih high level input voltage 2.7 v v cc 3.6 v 2.0 ? v cc + 0.3 v v il low level input voltage 2.7 v v cc 3.6 v ? 0.3 * ? 0.8 v * ? 2 v (pulse width lower than 20 ns) dc characteristics (ta = 0 to 70 ? , v cc = 2.7 v to 3.6 v) symbol parameter condition min typ. max unit i il input leakage current v in = 0 v to v cc ? ? 10 a i lo output leakage current v out = 0 v to v cc ? ? 10 a psl = gnd or nu ? 10 30 i cco0 * power on reset current psl = v cc , ffh command input after power on ? 10 30 ma i cco1 serial read current ce = v il , i out = 0 ma, tcycle = 50 ns ? 10 30 ma i cco2 programming current ? ? 10 30 ma i cco3 erasing current ? ? 10 30 ma i ccs1 standby current ce = v ih , wp =0 v/v cc , psl = 0 v/v cc /nu ? ? 1 ma i ccs2 standby current ce = v cc ? 0.2 v, wp = 0 v/v cc , psl = 0v/v cc /nu ? 10 50 a v oh high level output voltage i oh = ? 0.4 ma (2.7 v v cc 3.6 v) 2.4 ? ? v v ol low level output voltage i ol = 2.1 ma (2.7 v v cc 3.6 v) ? ? 0.4 v i ol ( by / ry ) output current of by / ry pin v ol = 0.4 v (2.7 v v cc 3.6 v) ? 8 ? ma * refer to application note (2) for detail free datasheet http:///
toshiba confidential TC58NVG2D4BFT00 2004-07-13c 5 ac characteristics and recommended operating conditions (ta = 0 to 70 ? , v cc = 2.7 v to 3.6 v) symbol parameter min max unit notes t cls cle setup time 0 ? ns t clh cle hold time 10 ? ns t cs ce setup time 0 ? ns t ch ce hold time 10 ? ns t wp write pulse width 25 ? ns t als ale setup time 0 ? ns t alh ale hold time 10 ? ns t ds data setup time 20 ? ns t dh data hold time 10 ? ns t wc write cycle time 50 ? ns t wh we high hold time 15 ? ns t ww wp high to we low 100 ? ns t rr ready to re falling edge 20 ? ns t rw ready to we falling edge 20 ? ns t rp read pulse width 35 ? ns t rc read cycle time 50 ? ns t rea re access time ? 35 ns t cea ce access time ? 45 ns t clea cle access time ? 45 ns t alea ale access time ? 45 ns t oh data output hold time 10 ? ns t rhz re high to output high impedance ? 30 ns t chz ce high to output high impedance ? 20 ns t reh re high hold time 15 ? ns t ir output-high-impedance-to- re falling edge 0 ? ns t rhw re high to we low 30 ? ns t whc we high to ce low 30 ? ns t whr we high to re low 30 ? ns t r memory cell array to starting address ? 50 s t dcbsyr1 data cache busy in read cache (following 31h and 3fh) ? 50 s t dcbsyr2 data cache busy in page copy (following 3ah) ? 55 s t wb we high to busy ? 200 ns t rst device reset time (ready/read/program/erase) ? 6/6/10/500 s free datasheet http:///
toshiba confidential TC58NVG2D4BFT00 2004-07-13c 6 ac test conditions condition parameter 2.7 v v cc 3.6 v input level 2.4 v, 0.4 v input pulse rise and fall time 3ns input comparison level 1.5 v, 1.5 v output data comparison level 1.5 v, 1.5 v output load c l (100 pf) + 1 ttl note: busy to ready time depends on the pull-up resistor tied to the by / ry pin. (refer to application note (9) toward the end of this document.) programming and erasing characteristics (ta = 0 to 70 ? , v cc = 2.7 v to 3.6 v) symbol parameter min typ. max unit notes t prog average programming time ? 800 2000 s t dcbsyw data cache busy time in write cache ? ? 2000 s (2) t dcmpw data cache busy time in multi page programming ? 5 10 s n number of partial program cycles in the same page ? ? ? (1) t berase block erasing time ? 3 10 ms (1) refer to application note (12) toward the end of this document. (2) t dcbsyw depends on the timing between internal programming time and data in time. free datasheet http:///
toshiba confidential TC58NVG2D4BFT00 2004-07-13c 7 timing diagrams latch timing diagram for command/address/data command input cycle timing diagram cle ale ce re we hold time t dh setup time t ds i/o : v ih or v il t cs t dh t ds t als t alh t wp t cls t ch t clh : v ih or v il ce cle we ale i/o free datasheet http:///
toshiba confidential TC58NVG2D4BFT00 2004-07-13c 8 address input cycle timing diagram data input cycle timing diagram : v ih or v il we t wp t wp t wh t wp t als t wc t dh t ds d in 0 d in 1 t clh t ch ale cle ce i/o d in 2111 t dh t ds t dh t ds pa16 to 17 pa8 to 15 ca8 to 11 : v ih or v il t dh t ds t cls cle t als t alh t wp t wh t wp ca0 to 7 t dh t ds t cs t wc ce we ale i/o t dh t ds t wp t wh t wc t dh t ds t wp t wh t wc t dh t ds t wp t wh t wc pa0 to 7 free datasheet http:///
toshiba confidential TC58NVG2D4BFT00 2004-07-13c 9 serial read cycle timing diagram status read cycle timing diagram t reh t chz ce t rhz t rea t rc t rr t rhz t rea t rhz t rea re by / ry i/o t oh t oh t oh t rp t rp t rp t cea t whr we t dh t ds t cls t clea t cs t clh t ch t wp status output 70h * t whc t cea t ir t rea t rhz t chz ce cle re by / ry i/o : v ih or v il t oh * : 70h represents the hexadecimal number free datasheet http:///
toshiba confidential TC58NVG2D4BFT00 2004-07-13c 10 read cycle timing diagram read cycle timing diagram: when interrupted by 30h pa16 to 17 pa8 to 15 pa0 to 7 ca8 to 11 ca0 to 7 i/o t cs t cls t clh t ch t dh t ds t wc t als t alh we cle ce ale re t dh t ds t dh t ds t dh t ds t dh t ds t alh t clea t r t dh t ds t wb t cs t cls t clh t ch t als t rc t rr t rea t cea col. add. n data out from col. add. n t dh t ds 00h d out n d out n + 1 ce 30h pa16 to 17 pa8 to 15 pa0 to 7 ca8 to 11 ca0 to 7 i/o t cs t cls t clh t ch t dh t ds t wc t als t alh we cle ce ale re t dh t ds t dh t ds t dh t ds t dh t ds t alh t clea t r t dh t ds t wb t cs t cls t clh t ch t als t rc t rr t rea t cea col. add. n t dh t ds 00h d out n d out n + 1 by / ry t chz t rhz t oh col. add. n by / ry free datasheet http:///
toshiba confidential TC58NVG2D4BFT00 2004-07-13c 11 read cycle with data cache timing diagram (1/2) 30h pa16 to 17 pa8 to 15 pa0 to 7 ca8 to 11 ca0 to 7 i/o t dh t ds t wc t als t alh we cle ce ale re t dh t ds t dh t ds t dh t ds t dh t ds t alh t r t dh t ds t wb t cs t cls t clh t ch t als t rc t rr t rea column address n * t dh t ds 00h d out n d out 1 by / ry t cea page address m d out 31h t dh t ds t wb t dcbsyr1 31h t dh t ds t wb d out 0 t rr t rea t dcbsyr1 t cs t cls t clh t ch t clea t cs t cls t clh t ch t clea t cea page address m col. add. 0 col. add. 0 page address m + 1 t rw t cs t cls t clh t ch 1 continues to of next page 1 * the column address will be reset to 0 by the 31h command input. free datasheet http:///
toshiba confidential TC58NVG2D4BFT00 2004-07-13c 12 read cycle with data cache timing diagram (2/2) continues from of next page 1 i/o we cle ce ale re by / ry d out t clea t wb 31h t dh t ds t cs t cls t clh t ch t wb 31h t dh t ds t cs t cls t clh t ch t rc t rr t rea page address m + 1 row address m + x t clea t wb t rc t rr t rea t cea 3fh t dh t ds t cs t cls t clh t ch d out 0 d out 1 d out t rc t rr t rea t cea page address m + 2 t dcbsyr1 t dcbsyr1 t dcbsyr1 t clea col. add. 0 col. add. 0 col. add. 0 t cea d out 0 d out 1 d out d out 0 d out 1 d out 1 free datasheet http:///
toshiba confidential TC58NVG2D4BFT00 2004-07-13c 13 column address change in read cycle timing diagram (1/2) t clea i/o t cs t cls t clh t ch t wc t als t alh t r cle ce ale re t dh t ds t dh t ds column address a t alh t wb t cs t cls t clh t ch t als t rc t rea t cea t rr page address p page address p column address a 00h ca0 to 7 t dh t ds ca8 to 11 t dh t ds pa0 to 7 t dh t ds pa8 to 15 t dh t ds pa16 to 17 t dh t ds 30h d out a d out a + 1 d out a + n we 1 continues from of next page 1 by / ry free datasheet http:///
toshiba confidential TC58NVG2D4BFT00 2004-07-13c 14 column address change in read cycle timing diagram (2/2) i/o t cs t cls t clh t ch 05h ca0 to 7 ca8 to 11 t wc t als t alh cle ce ale re t dh t ds t dh t ds t dh t ds column address b e0h t dh t ds t alh t cs t cls t clh t ch t als t rea d out a + n t rhw page address p column address b t rc t clea t cea t ir d out b + n? d out b + 1 d out b 1 continues from of next page 1 we by / ry free datasheet http:///
toshiba confidential TC58NVG2D4BFT00 2004-07-13c 15 auto-program operation timing diagram ca0 to 7 t cls t cls t als t ds t dh we cle ce ale re by / ry : v ih or v il t clh t ch t cs t ds t dh t alh i/o : do not input data while data is being output. t cs t dh t ds t dh t prog t wb t ds t alh t als * ) m: up to 2112 (byte input data for 8 device). column address n ca8 to 11 d in n d in d in m * 10h 70h status output pa0 to 7 pa8 to 15 pa16 to 17 80h free datasheet http:///
toshiba confidential TC58NVG2D4BFT00 2004-07-13c 16 auto-program operation with data cache timing diagram (1/3) (note) make sure to terminate the operation with 80h-10h- command sequence. if the operation is terminated by 80h-15h command sequence, monitor i/o 6 (ready / busy) by issuing status read command (70h) and make su re the previous page program operation is completed. if the page program operation is comp leted issue ffh reset before next operation. t cls t als t ds t dh 80h we cle ce ale re by / ry : v ih or v il t clh t ch t cs t cls t ds t dh t alh i/o : do not input data while data is being output. t cs t dh t ds t dh t dcbsyw d in 0 d in 1 t wb 80h t ds 15h t alh t als d in 2111 1 continues to 1 of next page pa16 to 17 ca0 to ca11 is 0 in this diagram. ca0 to 7 ca0 to 7 ca8 to 11 pa0 to 7 pa8 to 15 free datasheet http:///
toshiba confidential TC58NVG2D4BFT00 2004-07-13c 17 auto-program operation with data cache timing diagram (2/3) t cls t als t ds t dh ca0 to 7 80h we cle ce ale re by / ry t clh t ch t cs t cls t ds t dh t alh i/o : v ih or v il : do not input data while data is being output. pa0 to 7 ca8 to 11 t cs 1 continued from 1 of last page t dh t ds t dh t dcbsyw d in 0 d in 1 t wb 80h t ds 15h t alh t als d in 2111 pa16 to 17 2 pa8 to 15 ca0 to 7 repeat a max of 126 times (in order to program pages 1 to 126 of a block). free datasheet http:///
toshiba confidential TC58NVG2D4BFT00 2004-07-13c 18 auto-program operation with data cache timing diagram (3/3) 70h t cls t als t ds t dh we cle ce ale re by / ry : v ih or v il t clh t ch t cs t cls t ds t dh t alh i/o : do not input data while data is being output. t cs 2 t dh t ds t dh t prog ( * 1) t wb t ds t alh t als d in 2111 continued from 2 of last page ( * 1) t prog : since the last page programming by 10h command is initiated after the previous cache program, the t prog during cache programming is given by the following equation. t prog = t prog of the last page + t prog of the previous page ? a a = (command input cycle + address input cycle + data input cycle time of the last page) if ?a? exceeds the t prog of previous page, t prog of the last page is 2000 s max. 80h ca0 to 7 ca8 to 11 pa0 to 7 pa8 to 15 pa16 to 17 d in 0 d in 1 10h status free datasheet http:///
toshiba confidential TC58NVG2D4BFT00 2004-07-13c 19 multi-page program operation with data cache timing diagram (1/4) (note) make sure to terminate the operation with 80h-10h- command sequence. if the operation is terminated by 80h-15h command sequence, monitor i/o 6 (ready / busy) by issuing status read command (70h) and make sure the previous page program operation is completed. if the page program operation is completed issue ffh reset before next operation. t cls t als t ds t dh 80h we cle ce ale re by / ry : v ih or v il t clh t ch t cs t cls t ds t dh t alh i/o : do not input data while data is being output. t cs t dh t ds t dh t dcmpw d in 0 d in 1 t wb 80h t ds 11h t alh t als d in 2111 1 continues to 1 of next page pa16 to 17 ca0 to ca11 is 0 in this diagram. pa17 is 0 in this diagram. ca0 to 7 ca0 to 7 ca8 to 11 pa0 to 7 pa8 to 15 page address m free datasheet http:///
toshiba confidential TC58NVG2D4BFT00 2004-07-13c 20 multi-page program operation with data cache timing diagram (2/4) t cls t als t ds t dh ca0 to 7 80h we cle ce ale re by / ry t clh t ch t cs t cls t ds t dh t alh i/o : v ih or v il : do not input data while data is being output. pa0 to 7 ca8 to 11 t cs 1 continued from 1 of last page t dh t ds t dh t dcbsyw d in 0 d in 1 t wb 80h t ds 15h t alh t als d in 2111 pa16 to 17 2 pa8 to 15 ca0 to 7 repeat a max of 127 times (in order to program pages 0 to 126 of a block). page address m ca0 to ca11 is 0 in this diagram. pa17 is 1 in this diagram. free datasheet http:///
toshiba confidential TC58NVG2D4BFT00 2004-07-13c 21 multi-page program operation with data cache timing diagram (3/4) t cls t als t ds t dh 80h we cle ce ale re by / ry : v ih or v il t clh t ch t cs t cls t ds t dh t alh i/o : do not input data while data is being output. t cs t dh t ds t dh t dcmpw d in 0 d in 1 t wb 80h t ds 11h t alh t als d in 2111 3 continues to 3 of next page pa16 to 17 ca0 to 7 ca0 to 7 ca8 to 11 pa0 to 7 pa8 to 15 page address m+1 2 ca0 to ca11 is 0 in this diagram. pa17 is 0 in this diagram. free datasheet http:///
toshiba confidential TC58NVG2D4BFT00 2004-07-13c 22 multi-page program operation with data cache timing diagram (4/4) ( * 1) t prog : since the last page programming by 10h command is initiated after the previous cache program, the t prog during cache programming is given by the following equation. t prog = t prog of the last page + t prog of the previous page ? a a = (command input cycle + address input cycle + data input cycle time of the last page) if ?a? exceeds the t prog of previous page, t prog of the last page is 2000 s max. 71h t cls t als t ds t dh we cle ce ale re by / ry : v ih or v il t clh t ch t cs t cls t ds t dh t alh i/o : do not input data while data is being output. t cs 3 t dh t ds t dh t prog ( * 1) t wb t ds t alh t als d in 2111 continued from 3 of last page 80h ca0 to 7 ca8 to 11 pa0 to 7 pa8 to 15 pa16 to 17 d in 1 10h status d in 0 page address m+1 ca0 to ca11 is 0 in this diagram. pa17 is 1 in this diagram. free datasheet http:///
toshiba confidential TC58NVG2D4BFT00 2004-07-13c 23 auto block erase timing diagram multi block erase timing diagram t cs 60h pa8 to 15 we cle ce ale re by / ry : v ih or v il t cls t clh t cls pa0 to 7 t ds t dh t als : do not input data while data is being output. auto block erase setup command i/o d0h 70h t wb t berase busy status read command erase start command status output t alh pa16 to 17 t cs 60h pa8 to 15 we cle ce ale re by / ry : v ih or v il t cls t clh t cls pa0 to 7 t ds t dh t als : do not input data while data is being output. i/o d0h 71h t wb t berase busy status read command status output t alh pa16 to 17 1 2 repeat for 2 blocks 1 st block : pa17 = 0 2 nd block : pa17= 1 free datasheet http:///
toshiba confidential TC58NVG2D4BFT00 2004-07-13c 24 id read operation timing diagram : v ih or v il we cle re t cea ce ale i/o t alea id read command address 00 maker code device code t rea t cls t cs t dh t ch t alh t als t cls t cs t ch t alh t dh 90h 00h 98h t rea dch t rea t rea see table 5 see table 5 free datasheet http:///
toshiba confidential TC58NVG2D4BFT00 2004-07-13c 25 page copy(2) (1/4) (note) make sure wp is held to high level when page copy (2) operation is performed. also make sure the page copy operation is terminated with 8ch-10h command sequence. i/o t cs t cls t clh t ch 00h ca0 to 7 ca8 to 11 pa8 to 15 t dh t ds t wc t als t alh we cle ce ale re t dh t ds t dh t ds t dh t ds pa0 to 7 t dh t ds t alh t clea 30h t dh t ds t wb t cs t cls t clh t ch t als t rc t rr col. add.= 0 data out from col. add. = 0 pa16 to 17 t dh t ds 1 t r d out 1 d out 0 t cea t rea 2111 page address n by ry/ free datasheet http:///
toshiba confidential TC58NVG2D4BFT00 2004-07-13c 26 page copy(2) (2/4) continues to 2 of next page t cls t als t ds t dh ca0 to 7 8ch t clh t ch t cs t ds t dh t alh : v ih or v il : do not input data while data is being output. pa0 to 7 ca8 to 11 t cs t dh t ds t dh t dcbsyw d in 0 t wb 00h t ds 15h t alh t als d in 2111 pa16 to 17 pa8 to 15 ca0 to 7 re ale we ce i/o by / ry cle 1 2 continued from 1 of last page page address m d in 1 col. add. = 0 data input is required only if prev ious data output needs to be altered. if the data has to be changed, locate the desired address with the column address input after the 8ch command, and change only the data that needs be changed. if the data does not have to be changed, data input cycles are not required. can be repeated until data change is completed. can be repeated from page 0 to 126 within a block t cls free datasheet http:///
toshiba confidential TC58NVG2D4BFT00 2004-07-13c 27 page copy(2) (3/4) continues to 3 of next page i/o t cs t cls t clh t ch 00h ca0 to 7 ca8 to 11 pa8 to 15 t dh t ds t wc t als t alh we cle ce ale re t dh t ds t dh t ds t dh t ds pa0 to 7 t dh t ds t alh t clea 3ah t dh t ds t wb t cs t cls t clh t ch t als t rc t rr col. add. = 0 data out from col. add. = 0 pa16 to 17 t dh t ds t dcbsyr2 d out 1 d out 0 t cea t rea 2111 page address n + 1 2 3 continued from 2 of last page can be repeated from page 0 to 126 within a block by ry/ free datasheet http:///
toshiba confidential TC58NVG2D4BFT00 2004-07-13c 28 page copy(2) (4/4) t cls t als t ds t dh ca0 to 7 8ch we cle ce ale re t clh t ch t cs t cls t ds t dh t alh i/o pa0 to 7 ca8 to 11 t cs pa8 to 15 t dh t ds t dh t prog ( * 1) d in 0 d in 1 t wb 70h t ds t alh t als d in 2111 3 continued from 3 of last page pa16 to 17 : v ih or v il : do not input data while data is being output. can be repeated until data change is completed. ( * 1) t prog : since the last page programming by 10h comm and is initiated after the previous cache program, the t prog during cache programming is gi ven by the following equation. t prog = t prog of the last page + t prog of the previous page-a a = (command input cycle + address input cycle + data input cycle time of the last page) if ?a? exceeds the t prog of previous page, t prog of the last page is 2000 s max. status 10h by ry/ free datasheet http:///
toshiba confidential TC58NVG2D4BFT00 2004-07-13c 29 pin functions the device is a serial access memory which utiliz es time-sharing input of address information. command latch enable: cle the cle input signal is used to control loading of the operation mode command into the internal command register. the command is latched into the command regi ster from the i/o port on the rising edge of the we signal while cle is high. address latch enable: ale the ale signal is used to control loading address in formation into the internal address register. address information is latched into the address register from the i/o port on the rising edge of we while ale is high. chip enable: the device goes into a low-power standby mode when ce goes high during the device is in ready state. the ce signal is ignored when device is in busy state ( by / ry = l), such as during a program or erase or read operation, and will not enter standby mode even if the ce input goes high. write enable: the we signal is used to control the acqu isition of data from the i/o port. read enable: the re signal controls serial data output. data is available t rea after the falling edge of re . the internal column address counter is also increme nted (address = address + l) on this falling edge. i/o port: i/o1 to 8 the i/o1 to 8 pins are used as a port for transferring address, command and input/ output data to and from the device. write protect: the wp signal is used to protect the de vice from accidental programming or erasing. the internal voltage regulator is reset when wp is low. this signal is usua lly used for protecting the data during the power-on/off sequence when input signals are invalid. ready/busy: the by / ry output signal is used to indicate th e operating condition of the device. the by / ry signal is in busy state ( by / ry = l) during the program, erase and read operations and will return to ready state ( by / ry = h) after completion of the operation. the output buff er for this signal is an open drain and has to be pulled-up to vccq with an appropriate resister. power on select: psl the psl signal is used to select wh ether the device initialization should take place during the device power on or during the first reset. please refer to the application note (2) for details. ce we re wp by / ry free datasheet http:///
toshiba confidential TC58NVG2D4BFT00 2004-07-13c 30 schematic cell layout and address assignment the program operation works on page units wh ile the erase operation works on block units. a page consists of 2112 bytes in which 2048 bytes are used for main memory storage and 64 bytes are for redundancy or for other uses. 1 page = 2112 bytes 1 block = 2112 bytes 128 pages = (256k + 8k) bytes capacity = 2112 bytes 128pages x 2048blocks table 1. addressing i/o8 i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 first cycle ca7 ca6 ca5 ca4 ca3 ca2 ca1 ca0 second cycle l l l l ca11 ca10 ca9 ca8 third cycle pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 ca0 to ca11: column address pa0 to pa17: page address pa7 to pa17: block address pa0 to pa6: nand address in block fourth cycle pa15 pa14 pa13 pa12 pa11 pa10 pa9 pa8 fifth cycle l l l l l l pa17 pa16 2112 262144 pages 2048 blocks 2048 2048 64 64 page buffer data cache i/o8 i/o1 128 pages = 1 block 8i/o free datasheet http:///
toshiba confidential TC58NVG2D4BFT00 2004-07-13c 31 operation mode: logic and command tables the operation modes such as program, erase, read and reset are controlled by command operations shown in table 3. address input, comma nd input and data input/output are controlled by the cle, ale, ce , we , re and wp signals, as shown in table 2. table 2. logic table cle ale ce we re wp * 1 psl * 3 command input h l l h * 0v/ v cc/ nu data input l l l h h 0v/ v cc/ nu address input l h l h * 0v/ v cc/ nu serial data output l l l h * 0v/ v cc/ nu during program (busy) * * * * * h 0v/ v cc/ nu during erase (busy) * * * * * h 0v/ v cc/ nu * * h * * * 0v/ v cc/ nu during read (busy) * * l h ( * 2) h ( * 2) * 0v/ v cc/ nu program, erase inhibit * * * * * l 0v/ v cc/ nu standby * * h * * 0 v/v cc 0v/ v cc/ nu h: v ih , l: v il , * : v ih or v il * 1: refer to application note (10) toward the end of this document regarding the wp signal when program or erase inhibit * 2: if ce is low during read busy, we and re must be held high to avoid unintended co mmand/address input to the device or read to device. reset or status read command can be input during read busy. * 3: psl must be tied to either 0v or vcc, or left unconnected (nu). free datasheet http:///
toshiba confidential TC58NVG2D4BFT00 2004-07-13c 32 table 3. command table (hex) first cycle second cycle acceptable while busy serial data input 80 ? read 00 30 column address change in serial data output 05 e0 read with data cache 31 ? read start for last page in read cycle with data cache 3f ? auto page program 80 10 column address change in serial data input 85 ? auto program with data cache 80 15 multi page program 80 11 read for page copy (2) 00 3a auto program with data cache during page copy (2) 8c 15 auto program for last page during page copy (2) 8c 10 auto block erase 60 d0 id read 90 ? status read 70 ? { status read for multi-page program or multi block erase 71 ? { reset ff ? { table 4 shows the operation states for read mode. table 4. read mode operation states cle ale ce we re i/o1 to i/o8 power output select l l l h l data output active output deselect l l l h h high impedance active h: v ih , l: v il , * : v ih or v il hex data bit assignment (example) 1 0 0 0 0 0 0 0 8 7 6 5 4 3 2 i/o1 serial data input: 80h free datasheet http:///
toshiba confidential TC58NVG2D4BFT00 2004-07-13c 33 device operation read mode read mode is set when the "00h" and ?30h? commands are issued to th e command register. between the two commands, a start address for the read mode needs to be issued. refer to the figures below for the sequence and the block diagram (refer to the detailed timing chart.). random column address change in read cycle by / ry we cle re 00h ce ale i/o busy 30h page address n column address m m m+1 m+2 page address n t r start-address input a data transfer operation from the cell array to the data cache via page buffer starts on the rising edge of we in the 30h command input cycle (after the address information has been latched). the device will be in the busy state during this transfer period. after the transfer period, the device returns to ready state. serial data can be output synchronously with the re clock from the start address designated in the address input cycle. cell array select page n m m data cache page buffer i/o1 to 8: m = 2111 start-address input select page n m by / ry we cle 00h ce ale i/o col. m page n m? busy page n 30h 05h e0h col. m? m m + 1 m? m? + 1 m? + 2m? + 3m? + 4 page n col. m start from col. m start from col. m? during the serial data output from the data cache, the column address can be changed by inputting a new column address using the 05h and e0h commands. the data is read out in serial starting at the new column address. random column address change operation can be done multiple times within the same page. t r m + 2m + 3 re free datasheet http:///
toshiba confidential TC58NVG2D4BFT00 2004-07-13c 34 read operation with read cache the device has a read operation with data cache that enables the high speed read oper ation shown below. when the block address changes, this sequence has to be started from the beginning. page n + 2 if the 31h command is issued to the device, the data content of t he next page is transferred to the page buffer during serial d ata out from the data cache, and therefore the tr (data transfer from memory cell to data register) will be reduced. 1 normal read. data is transferred from page n to data cache through page buffer. during this time period, the device outputs b usy state for 50 s max (tr). 2 after the ready/busy returns to ready, 31h command is issued a nd data is transferred to data cache from page buffer again. th is data transfer takes 50 us max (tdcbsyr1) and the completion of this time period can be det ected by read/busy signal. 3 data of page n + 1 is transferred to page buffer from cell while the data of p age n in data cache can be read out by /re clock simultaneously. 4 the 31h command makes data of page n + 1 transfer to data cache from page buffer after the completi on of the transfer from cell to page buffer. the device outputs bu sy state for 50 s max. (tdcbsyr1). this busy period depends on the co mbination of the internal data transfer time from cell to page buffer and the ser ial data out time. 5 data of page n + 2 is transferred to page buffer from cell while the data of page n + 1 in data cache can be read out by /re clock simultaneously 6 the 3fh command makes the data of page n + 2 transfer to the data cache from the page buffer after the co mpletion of the transfer from cell to page buffer. the device ou tputs busy state for 50 s max. (tdcbsyr1). this busy period depends on the combination of the internal data transfer time from cell to page buffer and th e serial data out time. 7 data of page n + 2 in data cache can be read out, but since the 3fh command does not transfer the data from the memory cell to page buffer, the device can accept new co mmand input immediately after the completion of serial data out. by / ry we cle 00h ce ale i/o t r 30h col. m page n 0 1 2 3 31h 31h 0 1 2 3 page address n column 0 2111 page address n + 1 2111 0 1 2 3 page address n + 2 2111 3fh data cache page buffer cell array 1 2 3 3 4 5 5 1 6 7 page n page n page n + 1 page n 30h 31h & re clock page n + 1 page n + 2 page n + 1 31h & re clock page n + 2 3fh & re clock 1 2 4 3 5 6 7 t dcbsyr1 t dcbsyr1 t dcbsyr1 re free datasheet http:///
toshiba confidential TC58NVG2D4BFT00 2004-07-13c 35 auto page program operation the device carries out an automatic page program operation when it receives a "10h" program command after the address and data have been input. the sequence of command, addr ess and data input is shown below. (refer to the detailed timing chart.) random column address change in auto page program operation the column address can be changed by the 85h command during the data input sequ ence of the auto page program operation. two address input cycles after the 85h command are reco gnized as a new column address for the data input. after the new data is input to the new column address, the 10h command initia tes the actual data program into the selected page automatically. the random column address change operation can be repeated multiple times within the same page. 80h page n col. m 85h din din 10h status din din din din col. m? din din 70h busy data input selected page readin g & verification program col. m col. m? the data is transferred (programmed) from the data cache via the page buffer to the selected page on the rising edge of we following input of the ?10h? command. after programming, the programmed data is transferred back to the page buffer to be automatically verified by the device. if the programming does not succeed, the program/verify operation is repeated by the device until success is achieved or until the maximum loop number set in the device is reached. selected page program data input read& verification cle 80h ale i/o page p ce we col. m din 10h 70h din din din data status out re by ry/ free datasheet http:///
toshiba confidential TC58NVG2D4BFT00 2004-07-13c 36 auto page program operation with data cache the device has an auto page program with data cache operation enabling the high speed program operat ion shown below. when the b lock address changes this sequenced has to be started from the beginning. by / ry cle ale i/o ce we page n 80h add add add add status output din 15h 70h din din page n + 1 80h add add add add 1 status output din 15h 70h din din page n + p 80h add add add add 3 4 status output din 10h 70h din din 5 6 data cache page buffer cell array page n + p 1 2 3 4 5 5 6 page n page n + 1 data for page n + p 3 add add add data for page n data for page n data for page n + 1 data for page n + 1 page n + p ? 1 t dcbsyw t dcbsyw t prog (note) issuing the 15h command to the device after serial data i nput initiates the program operation with data cache 1 data for page n is input to data cache. 2 data is transferred to the page buffer by the 15h command. during the transfer the ready/busy outputs busy state (t dcbsyw ). 3 data is programmed to the selected page while the data for page n + 1 is input to the data cache. 4 by the 15h command, the data in the data cache is transferred to the page buffer after the programming of page n is completed . the device output busy state from the 15h command until the data cache becomes empty. the duration of this peri od depends on timing between the internal programming of page n an d serial data input for page n + 1 (t dcbsyw : 2000 s max). 5 data for page n + p is input to the data cache while the data of the page n + p ? 1 is being programmed. 6 the programming with data cache is terminated by the 10h command. when the device becomes ready, it shows that the internal p rogramming of the page n + p is completed. note: since the last page programming by the 10h command is init iated after the previous cache program, the tprog during cache programming is given by the following; t prog = t prog for the last page + t prog of the previous page ? ( command input cycle + address input cycle + data input cycle time of the previous page) re 2 free datasheet http:///
toshiba confidential TC58NVG2D4BFT00 2004-07-13c 37 pass/fail status for each page programmed by the auto page programming with data cache operation can be detected by the status read operation. z i/o1 : pass/fail of the curr ent page program operation. z i/o2 : pass/fail of the previous page program operation. the pass/fail status on i/o1 and i/o2 ar e valid under the following conditions. z status on i/o1: page buffer ready/busy is ready state. the page buffer ready/busy is output on i/o6 by status read operation or by / ry pin after the 10h command z status on i/o2: data cache read/busy is ready state. the data cache ready/busy is output on i/o7 by status read operation or by / ry pin after the 15h command. 80h?15h 70h status out page 1 data cache busy page buffer busy page 1 page 2 70h 70h page 2 70h 80h?15h page n ? 1 80h?10h page n page n ? 1 page n 70h 80h?15h i/o2 => i/o1 => invalid invalid page 1 invalid page n ? 2 invalid page n ? 1 invalid page n ? 1 page n page 1 page 2 70h if the page buffer busy returns to ready before the next 80h command input, and if status read is done during this ready period, the status read provides pass/fail for page 2 on i/o1 and pass/fail result for page1 on i/o2 status out status out status out status out status out example) by ry/ pin free datasheet http:///
toshiba confidential TC58NVG2D4BFT00 2004-07-13c 38 multi page program with data cache the device has a multi page program with data cache operation, which enables ev en higher speed program operation compared to auto page program with data cache as shown below. when the block address changes (increments) this sequenced has to be started from the beginning. the sequence of command, address an d data input is shown below. (refer to the detailed timing chart.) after ?15h? or ?10h? program command is input to device , physical programing star ts as follows. for details of auto program with data cache, refer to ?auto page progra m with data cache?. by / ry data input command data input 0 to 2111 15 80 80 11 10 80 80 11 data input command address input (district 0) data input 0 to 2111 dummy program command data input command data input 0 to 2111 data input command data input 0 to 2111 address input (district 1) program with data cache command address input (district 0) dummy program command address input (district 1) auto page program command the data is transferred (programmed) from the page buffer to the selected page on the rising edge of -we following input of the ?15h? or ?10h? command. after programming, the programmed data is transferred back to the register to be automatically verified by the device. if the programming does not succeed, the program/verify operation is repeated by the device until success is achieved or until the maximum loop number set in the device is reached. selected page reading & verification program district 0 district 1 free datasheet http:///
toshiba confidential TC58NVG2D4BFT00 2004-07-13c 39 starting the above operation from 1s t page of the selected erase blocks , and then repeating the operation total 128 times with incrementing the page address in the blocks, and then input the last page data of the blocks, ?10h? command exec utes final programming. in this full sequence, the co mmand sequence is following. after the ?15h? or ?10h? command, the results of the above operation is shown through the ?71h?status read command. the status description is as below. status output i/o1 total pass/fail pass: 0 fail: 1 i/o2 district 0 chip status1 : pass/fail pass: 0 fail: 1 i/o3 district 1 chip status1 : pass/fail pass: 0 fail: 1 i/o4 district 0 chip status2 : pass/fail pass: 0 fail: 1 i/o5 district 1 chip status2 : pass/fail pass: 0 fail: 1 i/o6 ready/busy ready: 1 busy: 0 i/o7 data cache ready/busy ready: 1 busy: 0 i/o8 write protect protect: 0 not protect: 1 i/o1 describes total pass/fail condition of district 0 and 1. if one of the districts fails during program operation, it shows ?fail?. i/o2 to 5 shows the pass/fail condition of each district. for details on ?chip status1? and ?chip status2?, refer to section ?status read?. 10 or15 71 pass i/o status read command fail by / ry 15 15 10 15 80 80 80 80 11 11 11 11 80 80 80 80 1st 127th 128th free datasheet http:///
toshiba confidential TC58NVG2D4BFT00 2004-07-13c 40 internal addressing in relation with the districts to use multi page program operation, the internal addressing should be considered in relation with the district. ? the device consists from 2 districts. ? each district consists from 1024 erase blocks. ? the allocation rule is follows. district 0: block 0, block 1, block 2, block 3,, block 1023 ( pa17 = l) district 1: block 1024, block 1025, block 1 026, block 1027,, block 2047 (pa17 = h) address input restriction for the multi page program with data cache operation there are following restrictions in usin g multi page program with data cache; (restriction) maximum one block should be se lected from each district. same page address within two districts has to be selected. for example; (80) [district 0, page address 0x00000] (11) (80) [district 1, page address 0x10000] (15 or 10) (80) [district 0, page address 0x00001] (11) (80) [district 1, page address 0x10001] (15 or 10) (acceptance) there is no order limitation of th e district for the address input. for example, following operation is accepted; (80) [district 0] (11) (80) [district 1] (15 or 10) (80) [district 1] (11) (80) [district 0] (15 or 10) it requires no mutual address relation betw een the selected blocks from each district. operating restriction during the multi page program with data cache operation (restriction) the operation has to be terminated with ?10h? command. once the operation is started, no commands other than the commands shown in the timing diagram is allowed to be input except for status read command and rese t command. if ff reset command is input before write operation to odd page (e.g. page a ddress 0x00001, 0x1ffff), is complete, it may cause damage to data not only to the programmed page, but also to the adjacent even page (e.g. page addre ss 0x00000, 0x1fffe in this case). free datasheet http:///
toshiba confidential TC58NVG2D4BFT00 2004-07-13c 41 page copy (2) by using page copy (2), data in a page can be copied to another page after the data has been read out. page copy (2) operation is as following. 1 data for page n is transferred to the data cache. 2 data for page n is read out. 3 copy page address m is input and if the data needs to be changed, changed data is input. 4 using the 15h command, the data in the page buffer is programmed to page m. data for page n + p1 is transferred to the data cache. 5 after the ready state, data for page n + p1 is output from the data cache while the data of page m is being programmed. data cache page buffer cell array 1 2 3 4 5 page n data for page n data for page n when changing data, changed data is input. page m page n + p1 data for page n + p1 cle ale i/o ce we page n 00h add add add add 1 add 30h page m 8ch add add add add din 15h din din 3 4 add page n + p1 00h add add add add 3a 5 add dout dout dout dout dout dout dout dout 1 2 t r t dcbsyw t dcbsyr2 re by ry/ free datasheet http:///
toshiba confidential TC58NVG2D4BFT00 2004-07-13c 42 data cache page buffer cell array 6 7 8 page m data for page m + r1 data for page m + r1 data for page n + p2 data for page n + pn by / ry cle ale i/o ce we 8 9 page n + pn 00h add add add add 10 add 3ah dout dout dout dout page m + r1 8ch add add add add din 15h din din add page n + p2 00h add add add add 3ah add dout dout dout dout 2 8ch add 1 6 7 9 10 page m + r1 page n + p2 page n + p1 page m + rn ? 1 page n + pn page m + rn ? 1 6 copy page address (m + r1) is input and if the data needs to be changed, changed data is input. 7 after programming of page m is completed, data cache for page m + r1 is transferred to the page buffer. 8 by the 15h command, the data in the page buffer is programmed to page m + r1. data for page n + p2 is transferred to the data cache. 9 the data in the page buffer is programmed to page m + rn ? 1. data for page n + pn is transferred to the data cache. 10 data for page n + pn is output. t dcbsyw t dcbsyr2 t dcbsyr2 re free datasheet http:///
toshiba confidential TC58NVG2D4BFT00 2004-07-13c 43 notes: this operation needs to be executed within block 0 ? 1023 or block 1024 ? 2047. make sure wp is held to high level when page copy (2) operation is performed. also make sure the page copy operation is terminated with 8ch-10h command sequence. data cache page buffer cell array page m + rn ? 1 data for page n + rn data for page n + rn by / ry cle ale i/o ce we page m + rn 8ch add add add add din 10h din din add 70h dout 2 page n + pn 11 copy page address (m + rn) is input and if the data needs to be changed, changed data is input. 12 by issuing the 10h command, the data in the page buffer is programmed to page n + rn. note: since the last page programming by the 10h command is initiated after the previous cache program, the t prog here will be expected as the following, t prog = t prog for the last page + tprog of the previous page ? ( command input cycle + address input cycle + data input cy cle time of the previous page) 11 11 12 12 t prog ( note ) re free datasheet http:///
toshiba confidential TC58NVG2D4BFT00 2004-07-13c 44 auto block erase the auto block erase operation st arts on the rising edge of we after the erase start command ?d0h? which follows the erase setup command ?60h?. this two-cycle process for erase oper ations acts as an extra layer of protection from accidental erasure of data due to external noise. the de vice automatically executes the erase and verify operations. multi block erase the multi block erase operation starts by selecting two block addresses before d0h command as in below diagram. the device automatically executes the erase and verify operations and the result can be monitored by checking the status by 71h status read command. for details on 71h status read command, refer to section ?multi page program with data cache?. internal addressing in relation with the districts to use multi block erase operation, the internal addressing should be consider ed in relation with the district. ? the device consists from 2 districts. ? each district consists from 1024 erase blocks. ? the allocation rule is follows. district 0: block 0, block 1, block 2, block 3,, block 1023 ( pa17 = l) district 1: block 1024, block 1025, block 1 026, block 1027,, block 2047 (pa17 = h) address input restriction for the multi block erase there are following restrictions in using multi block erase (restriction) maximum one block should be se lected from each district. for example; (60) [district 0] (60) [district 1] (d0) (acceptance) there is no order limitation of th e district for the address input. for example, following operation is accepted; (60) [district 1] (60) [district 0] (d0) it requires no mutual address relation betw een the selected blocks from each district. make sure to terminate the operation with d0h command. if the operation needs to be terminated before d0h command input, input the ffh reset co mmand to terminate the operation. pass i/o fail by / ry 60 d0 70 block address input: 3 cycles status read command busy erase start command pass i/o fail by / ry 60 d0 71 block address input: 3 cycles pa17=0 status read command busy erase start command 60 block address input: 3 cycles pa17=1 free datasheet http:///
toshiba confidential TC58NVG2D4BFT00 2004-07-13c 45 id read the device contains id codes which can be used to iden tify the device type, the ma nufacturer, and features of the device. the id codes can be read out under the following timing conditions: table 5. code table description i/o8 i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 hex data 1st data maker code 1 0 0 1 1 0 0 0 98h 2nd data device code 1 1 0 1 1 1 0 0 dch 3rd data chip number, cell type, pgm page, write cache ? ? ? ? ? ? ? ? see table 4th data page size, block size, redundant size, organization ? ? ? ? ? ? ? ? see table 3rd data description i/o8 i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 internal chip number 1 2 4 8 0 0 1 1 0 1 0 1 cell type 2 level cell 4 level cell 8 level cell 16 level cell 0 0 1 1 0 1 0 1 reserved 0 or 1 0 0 or 1 0 or 1 90h 00h 98h dch see table 5 see table 5 for the specifications of the access times t rea , t cea and t alea refer to the ac characteristics. we cle re t cea ce ale i/o t alea t rea id read command address 00 maker code device code free datasheet http:///
toshiba confidential TC58NVG2D4BFT00 2004-07-13c 46 4th data description i/o8 i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 page size (without redundant area) 1 kb 2 kb 4 kb 8 kb 0 0 1 1 0 1 0 1 block size (without redundant area) 64 kb 128 kb 256 kb 512 kb 0 0 1 1 0 1 0 1 redundant area size (byte/512byte) 8 16 reserved reserved 0 0 1 1 0 1 0 1 organization 8 16 0 1 reserved 0 or 1 free datasheet http:///
toshiba confidential TC58NVG2D4BFT00 2004-07-13c 47 status read the device automatically implements the execution and verification of the program and erase operations. the status read function is used to monitor the ready/ busy status of the device, determine the result (pass /fail) of a program or erase operation, and determine whether the device is in protect mode. the device status is output via the i/o port using re after a ?70h? command input. the status read can also be used during a read operation to find out the ready/busy status. the resulting information is outlined in table 6. table 6. status output table definition page program block erase cache program read cache read i/o1 chip status1 pass: 0 fail: 1 pass/fail pass/fail invalid i/o2 chip status 2 pass: 0 fail: 1 invalid pass/fail invalid i/o3 not used 0 0 0 i/o4 not used 0 0 0 i/o5 not used 0 0 0 i/o6 page buffer ready/busy ready: 1 busy: 0 ready/busy ready/busy ready/busy i/o7 data cache ready/busy ready: 1 busy: 0 ready/busy ready/busy ready/busy i/o8 write protect not protected :1 protected: 0 write protect write protect write protect the pass/fail status on i/o1 and i/o2 is only valid during a prog ram/erase operation when the device is in the ready state. chip status 1: during a auto page program or auto block erase operation this bit indicates the pass/fail result. during a auto page programming with data cache op eration, this bit shows the pass/fail results of the current page program operation, and therefore this bit is only valid when i/o6 shows the ready state. chip status 2: this bit shows the pass/fail result of the previous page program operat ion during auto page programming with data cache. this status is va lid when i/o7 shows the ready state. the status output on the i/o6 is th e same as that of i/o7 if the comma nd input just before the 70h is not 15h or 31h. free datasheet http:///
toshiba confidential TC58NVG2D4BFT00 2004-07-13c 48 an application example with multiple de vices is shown in the figure below. system design note: if the by / ry pin signals from multiple devices are wired together as shown in the diagram, the status read function can be used to determine the status of each individual device. reset the reset mode stops all operations. for example, in ca se of a program or erase operation, the internally generated voltage is discharged to 0 volt and the device enters the wait state. reset during a cache program/page copy may not just stop the most recent page program but it may also stop the previous program to a page de pending on when the ff reset is input. the response to a ?ffh? reset co mmand input during the various device operations is as follows: when a reset (ffh) command is input during programming internal v pp 80 10 ff 00 by / ry t rst (max 10 s) device 1 cle 1 ce device 2 2 ce device 3 3 ce device n n ce device n + 1 1 n ce + ale we re by / ry we re status on device 1 70h 1 ce ale i/o 70h status on device n by / ry cle n ce busy i/o1 to i/o8 free datasheet http:///
toshiba confidential TC58NVG2D4BFT00 2004-07-13c 49 when a reset (ffh) command is input during erasing when a reset (ffh) command is input during read operation when a reset (ffh) command is input during ready when a status read command (70h) is input after a reset when two or more reset commands are input in succession 10 by / ry ff ff (3) (2) (1) the second command is invalid, but the third command is valid. ff ff ff i/o status : pass/fail pass : ready/busy ready ff 70 by / ry 00 ff 00 by / ry t rst (max 6 s) 30 internal erase voltage d0 ff 00 by / ry t rst (max 500 s) 00 by / ry t rst (max 6 s) ff free datasheet http:///
toshiba confidential TC58NVG2D4BFT00 2004-07-13c 50 application notes and comments (1) power-on/off sequence: the timing sequence shown in the figure below is necessary for the power-on/off sequence. the device internal initialization starts after the po wer supply reaches an appropriate level in the power on sequence. during the initialization the device ready/busy signal indicates the busy state as shown in the figure below. in this time period, the acceptable commands are ffh or 70h. the wp signal is useful for protecting against data corruption at power-on/off. (2) power-on reset the device goes into automatic self initialization du ring power on if psl is tied either to gnd or nu. during the initialization pr ocess, the device consumes a maximum current of 30 ma (i cco0 ). if psl is tied to vcc, the device will not complete its self init ialization during power on and will not consume i cco0 , and completes the initialization process with the first re set command input after power on. during the first ffh reset busy period, the device consumes a maximum current of 30 ma (i cco0 ). in either case (psl = gnd/ nu or v cc ), the following sequence is necessary because so me input signals may not be stable at power-on. (3) prohibition of unspecified commands the operation commands are listed in t able 3. input of a command other th an those specified in table 3 is prohibited. stored data may be co rrupted if an unknown command is entered during the command cycle. (4) restriction of commands while in the busy state during the busy state, do not in put any command except 70h and ffh. v il operation 0 v v cc 2.7 v 2.5 v v il don?t care don?t care v ih ce , we , re wp cle, ale invalid don?t care ready/busy 1 ms max 100 s max ff reset power on free datasheet http:///
toshiba confidential TC58NVG2D4BFT00 2004-07-13c 51 (5) acceptable commands after serial input command ?80h? once the serial input command ?80h ? has been input, do not input an y command other than the column address change in serial data input command ?85h?, auto program command ?10h?, multi-page program command ?11h?, auto program with data cache command ?15h?, or the reset command ?ffh?. if a command other than ?85h?, ? 10h?, ?11h?, ?15h? or ?ffh? is in put, the program operation is not performed and the device operation is set to the mode which the input command specifies. (6) addressing for program operation within a block, the pages must be programmed consecut ively from the lsb (least significant bit) page of the block to msb (most significant bit) page of the bl ock. random page address programming is prohibited. command other than ?85h?, ?10h?, ?11h?, ?15h? or ?ffh? 80 programming cannot be executed. 10 xx mode specified by the command. we by / ry 80 ff address input data in: data (1) page 0 data register page 2 page 1 page 31 page 127 (1) (2) (3) (32) (128) data (128) from the lsb page to msb page data in: data (1) page 0 data register page 2 page 1 page 31 page 127 (2) (32) (3) (1) (128) data (128) ex.) random page program (prohibition) free datasheet http:///
toshiba confidential TC58NVG2D4BFT00 2004-07-13c 52 (7) status read during a read operation the device status can be read out by inputting the status read command ?70h? in read mode. once the device has been set to status read mode by a ?70h ? command, the device will not return to read mode unless the read command ?00h? is input during [a]. in this case, data output starts automatically from address n and address input is unnecessary (8) auto programming failure (9) by / ry : termination for the ready/busy pin ( by / ry ) a pull-up resistor needs to be used for termination because the by / ry buffer consists of an open drain circuit. fail 80 10 80 10 address m data input 70 i/o address n data input if the programming result for page address m is fail, do not try to program the page to address n in another block without the data input sequence. because the previous input data has been lost, the same input sequence of 80h command, address and data is necessary. 10 80 m n this data may vary fr om device to device. we recommend that you use this data as a reference when selecting a resistor value. v cc v cc device v ss r by / ry c l 1.5 s 1.0 s 0.5 s 0 1 k ? 4 k ? 3 k ? 2 k ? 15 ns 10 ns 5 ns t f t r r t r t f v cc = 3.3 v ta = 25c c l = 100 pf t f ready v cc 1.0 v t r 3.0 v 1.0 v busy 00 address n command ce we by / ry re [a] status read command input status read status output . 70 00 30 free datasheet http:///
toshiba confidential TC58NVG2D4BFT00 2004-07-13c 53 (10) note regarding the wp signal the erase and program operations are automatically reset when wp goes low. the operations are enabled and disabled as follows: enable programming disable programming enable erasing disable erasing wp t ww (100 ns min) 80 10 we by / ry din wp t ww (100 ns min) 60 d0 we by / ry din wp t ww (100 ns min) 80 10 we by / ry din wp t ww (100 ns min) 60 d0 we by / ry din free datasheet http:///
toshiba confidential TC58NVG2D4BFT00 2004-07-13c 54 (11) when six address cycles are input although the device may read in a sixth address, it is ignored inside the chip. read operation program operation cle address input 00h ce we ale i/o by / ry ignored 30h cle ce we ale i/o address input ignored 80h data input free datasheet http:///
toshiba confidential TC58NVG2D4BFT00 2004-07-13c 55 (12) several programming cycles on the same page (partial page program) this device does not support partial page programming. free datasheet http:///
toshiba confidential TC58NVG2D4BFT00 2004-07-13c 56 (13) invalid blocks (bad blocks) the device occasionally contains unusable blocks. therefore, the following issues must be recognized: at the time of shipment, all data bytes in a valid block are ffh. for bad blocks, all bytes are not in the ffh st ate. please do not perform an erase operation to bad blocks. it may be impossible to recover the bad block information if the information is erased. check if the device has any bad blocks after installation into the system. refer to the test flow for bad block detection. bad blocks which are detected by the test flow must be managed as unusable blocks by the system. a bad block does not affect the perfor mance of good blocks because it is isolated from the bit lines by select gates. the number of valid blocks at the time of shipment is as follows: min typ. max unit valid (good) block number 1968 ? 2048 block bad block test flow * 1: no erase operation is allowed to detected bad blocks bad block bad block pass read check start bad block * 1 block no. = 2048 end yes fail block no = 1 no block no. = block no. + 1 read check: read either column 0 or 2048 of the last page of each block. if the data of the column is not ff (hex), define the block as a bad block. free datasheet http:///
toshiba confidential TC58NVG2D4BFT00 2004-07-13c 57 (14) failure phenomena for prog ram and erase operations the device may fail during a program or erase operation. the following possible failure modes should be consid ered when implementing a highly reliable system. failure mode detection and countermeasure sequence block erase failure status read after erase block replacement page programming failure status read after program block replacement single bit programming failure ?1 to 0? ecc ? ecc: error correction code. 4 bit correction per 528bytes is necessary. ? block replacement program erase when an error occurs during an erase operation, prevent future accesses to this bad block (again by creating a table within the system or by using another appropriate scheme). (15) do not turn off the power before write/erase operation is complete. avoid using th e device when the battery is low. power shortage and/or power failure before wr ite/erase operation is complete will cause loss of data and/or damage to data. (16) if ff reset command is input before write operation to odd page (e.g. page address 0x00001, 0x1ffff), is complete, it may cause damage to data not only to the page which is being programmed, but also to the adjacent even page (e.g. page addre ss 0x0000, page 0x1fffe in this case). when an error happens in block a, try to reprogram the data into another block (block b) by loading from an external buffer. then, prevent further system accesses to block a ( by creating a bad block table or by using another appropriate scheme). block a block b error occurs buffer memory free datasheet http:///
toshiba confidential TC58NVG2D4BFT00 2004-07-13c 58 package dimensions weight: 0.53 g (typ.) free datasheet http:///
toshiba confidential TC58NVG2D4BFT00 2004-07-13c 59 revision history date rev. description 2003-10-30 1.00 original version 2004-01-20 1.10 deleted page copy (1) operation timing diagram & notes. p.28 deleted command table related to page copy (1). 2004-07-13 1.20 deleted x16 device from data sheet and all related diagram, notes, and description. added ?toshiba confidential? in all pages. added multi page program as new operation. p.1 added indication that the device is multi level cell. deleted x16 device information from organization. added auto program with cache and multi page program with cache in modes. changed number of valid blocks from 1958 to 1968. changed auto block erase time from 1.5ms to 3ms. deleted x16 device information from package. p.2 deleted x16 information from pin assignment. changed pin 6 from gnd to nc. deleted i/o9 to i/o16 from pin names. deleted gnd from pin names. p.3 deleted i/o16 from block diagram changed t opr to t a in absolute maximum rating. p.4 changed minimum valid blocks from 1958 to 1968 in valid blocks table. changed icco0 (power on reset current) condition from psl=gnd or nc to psl=gnd or nu. changed condition of iccs in dc characteristics. changed minor appearance in table dc characteristics. p.6 changed tprog, tdcbsyw max from tbd to 2000 s changed tberase typ from 1.5ms to 3m s. also changed max from tbd to 10ms. added new parameter tdcmpw. p.8 deleted x16 information related to number of data input cycles p.15 fixed typo in timing diagram. deleted x16 information related to number of data input cycles. p.16 added note related to termin ation of cache program operation. deleted x16 information related to number of data input cycles. p.17 fixed typo in timing diagram. deleted x16 information related to number of data input cycles. p.18 deleted x16 information related to number of data input cycles. p.24 deleted fifth data output cycle from id read operation. p.25 added note related to wp signal during page copy (2). p.26 deleted x16 information related to number of data input cycles. p.28 deleted x16 information related to number of data input cycles. p.29 deleted i/o 9 to i/o 16 information from pin functions. p.30 deleted x16 schematic cell layout and address assignment. p.31 added psl in logic t able and added explanation. p.32 added multi page programming and st atus read for multi page program in command table. deleted i/o9 to i/o 16 from hex data bit assignment. p.33 deleted x16 information related to number of data input cycles. p.43 added notes related to wp signal during page copy (2). p.45 deleted x16 information from id code table deleted 5 th cycle information from id read. changed explanation of 3 rd cycle. p.46 deleted 5 th cycle information from id read. fixed typo in id code table. p.47 fixed typo in status output table ( wp ) deleted i/o 9 to i/o 16 from status output table. p.50 changed psl state from nc to nu in description of power on read. free datasheet http:///
toshiba confidential TC58NVG2D4BFT00 2004-07-13c 60 p.51 changed description in comment (5) . p.56 changed number of valid blocks from 1958 to 1968 in table. p.57 added note (16). p.59 added revision history in datasheet. free datasheet http:///
toshiba confidential TC58NVG2D4BFT00 2004-07-13c 61 ? the information contained herein is subject to change without notice. ? the information contained herein is presented only as a guide for the applicati ons of our products. no responsibility is assumed by toshiba for any infringements of patents or other rights of the third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of toshiba or others. ? toshiba is continually working to improve the quality and reliability of its products. nevertheless, semiconductor devices in general can malfunction or fail due to their inhe rent electrical sensitivity and vulnerability to physical stress. it is the responsibility of the buyer, when utilizing toshiba produc ts, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage to property. in developing your designs, please ensure that toshiba products are used within s pecified operating ranges as set forth in the most recent toshiba products specific ations. also, please keep in mind the precautions and conditions set forth in the ?handling guide for semicon ductor devices,? or ?toshiba semiconductor reliability handbook? etc.. ? the toshiba products listed in th is document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuri ng equipment, industrial robotics, domestic appliances, etc.). these toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunc tion or failure of which may cause loss of human life or bodily injury (?unintended usage?). unintended usage include atomic energy control in struments, airplane or spaceship instruments, transportation instruments, traffic signa l instruments, combusti on control instruments, medical instruments, all types of safety devices, etc .. unintended usage of toshiba products listed in this document shall be made at th e customer?s own risk. ? the products described in this document are subject to the foreign exchange and foreign trade laws. ? toshiba products should not be embedded to the down stream products which are prohibited to be produced and sold, under any law and regulations. 030619eba restrictions on product use free datasheet http:///

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